FPGA RTL Engineer
We are innovating at every level of the stack – from chip, to microcode, to power delivery and cooling, to new algorithms and network architectures at the cutting edge of ML research. Our fully-integrated system delivers unprecedented performance because it is built from the ground up for deep learning workloads.
Cerebras is building a team of exceptional people to work together on big problems. Join us!
You will work with the hardware and software teams to design an FPGA sub-system for high performance IO interconnect using the latest FPGAs.
- Design the micro-architecture and protocols to meet the system performance requirements.
- Write the RTL for multiple blocks within the design and work with the verification team to test/debug the design.
- Bring up the design in the lab to validate functionality and performance.
Skills & Qualifications
- 3+ years relevant experience with bringing FPGA designs to production.
- Experience with large scale FPGA technologies and tool flows, including timing closure, floorplanning, debugging techniques, etc.
- In-depth knowledge of data center networking protocols, such as TCP/IP and RDMA preferred.
- Experience with high-speed interfaces and bus protocols such as PCIe, 100G Ethernet, high speed memories such as DDR4 and/or HBM.
Sunnyvale, California, United States
- Host IO:
- Headquarters/Sunnyvale Office