Lead Architect - Next Generation ASIC
Cerebras is developing a radically new chip and system to dramatically accelerate deep learning applications. Our system runs training and inference workloads orders of magnitude faster than contemporary machines, fundamentally changing the way ML researchers work and pursue AI innovation.
We are innovating at every level of the stack – from chip, to microcode, to power delivery and cooling, to new algorithms and network architectures at the cutting edge of ML research. Our fully-integrated system delivers unprecedented performance because it is built from the ground up for the deep learning workload.
Cerebras is building a team of exceptional people to work together on big problems. Join us!
- You will be the Chief Architect for the next generation of Cerebras ML wafer scale engines
- Lead hardware micro-architects to deliver the right tradeoffs for performance/watt/area
- Work with software teams to understand opportunities to deliver optimal performance
- Work with system teams to develop high performance system and memory interfaces
- Guide architecture team to accurately model and predict performance across a range of workloads
- Clearly articulate the hardware roadmap to executive staff, stakeholders and customers
- Drive alignment across all functions on key aspects of the architecture
Skills & Qualifications:
- World class computer architect, with 10+ years of experience
- Demonstrated leadership of high-performance computing, machine learning or related fields
- Capability to drive fundamental changes in computer architecture
- Detailed experience of many core designs
- Detailed knowledge of dataflow architectures and tradeoffs
- Strong technical leadership skills across hardware and software.
- Ability to lead end-to-end workload analysis from low level assembly instruction code to high level distributed algorithms.
- Experience with performance analysis on: CPUs, GPUs, TPU, parallel architectures / distributed systems, dataflow / spatial architectures, many-core multi-thread environments
- Experience with modeling and architecting a balanced optimized system across compute, memory and fabric.
- Excellent written and verbal communication skills. Demonstrated ability to clearly articulate complex architectural tradeoffs while taking into consideration the audience's technical knowledge.
- PhD or Master’s degree in Computer Science, Electrical Engineering, or equivalent,
- Headquarters/Los Altos Office